There has been conventionally known a technique that counts a period of a reference clock with a stable frequency generated using, for example, a crystal oscillator by a high-speed clock signal, and generates a clock signal by multiplying or dividing the period of the reference clock on the basis of the count value (refer to Patent Literature 1, for example). In this technique, a high-speed clock is generated by a ring oscillator including a plurality of delay elements which delay a pulse signal and are connected in a ring shape. Further, the high-speed clock generated by the ring oscillator is counted to generate a clock signal as output.
A delay time of each delay element included in a ring oscillator fluctuates by, for example, fluctuation of power supply voltage or thermal noise, and fluctuations are accumulated by the number of passed delay elements. Thus, in prior art, as the period of a clock signal to be output increases, the fluctuation of the period disadvantageously increases.
Patent Literature 1: JP-H7-183800-A (corresponding to U.S. Pat. No. 5,477,196)